MÔ PHỎNG TRANSISTOR HIỆU ỨNG TRƯỜNG DÂY NANO KẼM OXIT
Article Sidebar
Full Text: 
PDF
Abstract
We report the simulation results of the field-effect transistor (FET) with various gate structures in order to find the FETs having the best electrical properties. We changed the ?gate configuration" with different arrangement gates (single-gate, double-gate, ordinary triple-gate, Pi-gate, omega-gate and gate all around (GAA)). Based on the simulation data, we drawn the Volt-Ampere characteristics lines (I-V). Then, we calculated the physical parameters affecting the operation of FETs including: threshold voltage, subthreshold slope, saturation currents, the on-off current ratio. Our simulations showed that the gate all around structure has better properties than the other structures, especially this structure restricts the short-channel effects.
Tóm tắt
Article Details
Tài liệu tham khảo
Thompson, S. E., Parthasarathy, S., Moore’s law the future of Si microelectrics, Materials today, 9, 20, (2006).
Ju, S., Lee, K., Yoon, M. H., Facchetti, A., Marks, T. J., Janes, D. B., High performance ZnO nanowire field effect transistors with organic gate nanodielectrics: Effects of metal contacts and ozone treatment, Nanotechnology, 18, 1, (2007).
Park, W. I., Kim, J. S., Yi, G., Bae, M. H., Lee, H., Fabrication and electrical characteristics of high-performance ZnO nanorod field-effect transistors, Applied Physics Letter, 85, 5052, (2004).
nanoHUB - Multi-gate Nanowire FET (2008). (https://www.nanohub.org/resources/2704).
Colinge, J., Xiong, W., FETs and Other Multi-Gate Transistors, Springer US, (2008).
Sekigawa, T., Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate, Solid State Electronics, 27, 827, (1984).
Auth, C., Allen, C., et al, A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitor, IEEE Transactions on Nanotechnology, 131, (2012).
Park, J. T., Colinge, J. P., Diaz, C. H., Pi-gate SOI MOSFET, IEEE Electron Device Letters, 22, 405, (2001).
Li, Y., Chou, H. M., Lee, J. W., Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs, IEEE Transactions on Nanotechnology, 4, 510, (2005).
Song, J. Y., Choi, W. Y., Park, J. H., Lee, J. D., Park, B. G., Design optimization of gate-all-around (GAA) MOSFETs, IEEE Transactions on Nanotechnology, 5, 186, (2006).